There is disclosed in the related art a PLL (phase lock loop) that includes a reference signal generator, a control oscillator, a TDC (time to digital converter), a digital filter, a phase detector, an analog filter, an amplifier, a lock detector, and switches.
However, in the related art PLL, the TDC includes plural inverters, and quantization is performed by utilizing a delayed time between the inverters. Hence, the resolution of the related art PLL is restricted by the delayed time of the inverters of the TDC. Since the delayed time of the inverters has limitation, the resolution of the related art PLL is low due to an insufficient handling ability of the PLL with respect to a high clock frequency.